1. Field of the Invention
The invention in general relates to ferroelectric electronic memories and more particularly to an apparatus and method for reading and/or writing a ferroelectric storage element in a memory cell.
2. Statement of the Problem
It is well-known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the field remains. If the field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic "1" state, and polarization in the opposite direction with a logic "0" state. See, for example, the circuits described in U.S. Pat. No. 2,876,436 issued to J. R. Anderson on Mar. 3, 1959; U.S. Pat. No. 4,873,664 issued to S. Sheffield Eaton, Jr.; U.S. Pat. No. 5,029,128 issued to Haruki Toda; and U.S. Pat. No. 5,406,510 issued to Takashi Mihara, et. al. These circuits include memory cells arranged in rows and columns, each memory cell including at least one switch, a capacitor having a pair of plate electrodes, and the memory also including plate lines connected to one plate of the capacitor in each cell, bit lines connected to the other plate of the capacitor through the switch. In the latter three patents the switch is a transistor having a gate and a pair of source/drains. Each of the latter circuits also include word lines connected to the control gate of the transistor. The transistor acts as a switch controlled by its gate, to connect the capacitor to the bit line. Information is written into a memory cell by placing either a high or a low voltage on the bit line, turning the transistor on to connect the bit line to the capacitor, and placing a predetermined voltage between the high and low voltage on the plate line. The circuit of the Anderson patent is essentially the same, except the voltage applied to the bit line turns on the diode switch. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The memory cell is read by creating a voltage difference between the bit line and plate line and sensing in some manner the presence or absence of a ferroelectric switching charge or current caused by the switching of the ferroelectric.
A problem with the ferroelectric memories disclosed in the above references is that when a switching voltage is placed across the ferroelectric capacitor, a charge flows from the capacitor into the bit line prior to the switching of the ferroelectric. In the specific memories discussed above, this extra charge or current is due to the linear capacitance of the ferroelectric capacitor, which is often called the linear displacement current or linear charge, but shall be referred to herein as the linear current or linear charge for simplicity. This charge alters the voltage on the bit line to a voltage closer to the voltage on the plate line, and thus reduces the voltage available to switch the ferroelectric capacitor. That is, the voltage available to switch the ferroelectric capacitor is significantly less than the full voltage available in the circuit as determined by the supply voltage. This problem of the reduction of the voltage available to switch the ferroelectric material occurs in most other ferroelectric memory designs in addition to those discussed above, but has been discussed in terms of these particular memories to provide a clear illustration of the problem, and since these are the most common types of ferroelectric memories, and the fastest ferroelectric memories presently available use designs similar to the designs in these references. This problem can have many impacts on the memory: it can create a need for a higher supply voltage, it can slow the switching process, and can result in errors due to inaccurately reading to or writing to the memory, all of which either make the memory less efficient, less reliable, more expensive to manufacture or a combination thereof.
One solution to the above problem is disclosed in U.S. Pat. No. 4,888,733 issued to Kenneth J. Mobley. In the memory disclosed in the Mobley patent, each memory cell includes two transistors, and the cell is read by pulsing the ferroelectric capacitor first in one direction, and storing the resulting charge flow in a first linear capacitor, then pulsing the ferroelectric capacitor in the opposite direction and storing the resulting charge flow in a second linear capacitor, then comparing the charges in the two capacitors. The linear current flow cancels out in this process. However, the process is time consuming, resulting in a slow memory read time, and it also requires the extra circuitry including at least one additional transistor per memory cell as well as the extra transistors and capacitors in the sensing circuit.
It would be highly desirable to have a ferroelectric memory in which essentially the full supply voltage is applied to switch the ferroelectric material, and at the same time was essentially as fast and as simple as the memory of the Mihara patent referenced above, for example.
3. Solution to the Problem
The present invention solves the above problem by connecting the bit line to a current sink during the initial portion of a read cycle. The current sink draws off the linear charge from the bit line, allowing essentially the full voltage as determined by the supply voltage to be applied across the ferroelectric material.
As known in the art, a memory could also be designed with the high and low voltages interchanged. In this case, the problem would be rephrased as the bit line voltage being lowered by the linear current, and the current sink would be replaced with a current source which would maintain the bit line at essentially the full high voltage during the initial portion of a read cycle.
In the ferroelectric memories disclosed in the Eaton, Toda, and Mihara patents discussed above, as well as other ferroelectric memories, the bit line is precharged to zero volts by connection to ground prior to the initiation of the read cycle. In such memories, the invention may be implemented simply by maintaining the electrical connection to the precharge circuit into the initial portion of the read cycle. In other words, the disconnection from the precharge circuit is delayed until the voltage across the capacitor rises to essentially the full potential difference as determined by the supply voltage, and the majority of the linear charge flows into the bit line. Thus, the linear charge will be drained away to ground via the precharge circuit, and will not reduce the voltage across the ferroelectric capacitor.
The precharge circuit in conventional memories includes a transistor connecting the bit line to circuit ground. Preferably, the precharge signal applied to the precharge transistor is boosted, increasing the current flow through the transistor and accelerating the removal of charge from the bit line, thereby reducing the cycle time.
The invention provides a ferroelectric integrated circuit memory comprising: a memory cell comprising a ferroelectric memory element capable of storing a linear charge and a ferroelectric charge; a sense line connected to or connectable to the ferroelectric memory element; a current source/sink; a linear charge switch connected between the current source/sink and the sense line; and a linear charge switch control circuit connected to the linear charge switch for turning on the switch at the beginning of a read cycle for a time sufficient to drain at least a portion of the linear charge from the memory element and subsequently closing the linear charge switch before the ferroelectric charge completely flows to the current source/sink. Preferably, the sense line is selected from the group consisting of a bit line and a plate line. Preferably, the memory element is selected from the group consisting of a ferroelectric capacitor and a ferroelectric FET. Preferably, the linear charge switch is selected from the group consisting of a transistor and a diode.
In another aspect, the invention provides a ferroelectric integrated circuit memory comprising: a memory cell comprising a ferroelectric memory element; a bit line; a word line; a plate line, and a precharge signal line; a first switch connected to the word line for electrically connecting the bit line and the ferroelectric memory element in response to a word signal on the word line and for electrically disconnecting the bit line and the ferroelectric memory element when the word signal is terminated; a current source/sink; a second switch connected to the precharge signal line for electrically connecting and disconnecting the bit line and the current source/sink in response to a precharge signal on the precharge signal line and electrically disconnecting the bit line and the current source/sink when the precharge signal is terminated; and a signal generator for, during a single read cycle, providing the precharge signal, then the word signal, and subsequently terminating the precharge signal. Preferably, the current source/sink comprises a ground. Preferably, the plate line is at constant voltage equal to one-half the supply voltage of the memory and the current source/sink comprises a ground. Preferably, the first and second switches are first and second transistors, each having a gate, and the word line is connected to the gate of the first transistor and the precharge line is connected to the gate of the second transistor. Preferably, the word signal and the precharge signal are boosted above the supply voltage of the memory. Preferably, the signal generator terminates the precharge signal before the ferroelectric memory element begins to switch. Preferably, the signal generator terminates the precharge signal while the ferroelectric memory element is switching.
In a further aspect, the invention provides a ferroelectric integrated circuit memory comprising: a memory cell comprising a ferroelectric memory element; a sense line electrically connected to or connectable to the ferroelectric memory element; and a current source/sink electrically connectable to the sense line for removing electric charge from the sense line while the sense line is electrically connected to the ferroelectric memory element. Preferably, the current source/sink is a ground.
In still another aspect, the invention provides a ferroelectric integrated circuit memory comprising: a memory cell comprising a ferroelectric memory element; a conducting line connected to or connectable to the ferroelectric memory element; a precharge signal line; a current source/sink; a switch connected to the precharge signal line for electrically connecting and disconnecting the conducting line and the current source/sink in response to a precharge signal on the precharge signal line and electrically disconnecting the conducting line and the current source/sink when the precharge signal is terminated; and a signal generator for generating a precharge signal that is boosted above the supply voltage of the memory. Preferably, the current source/sink is a ground.
In yet another aspect, the invention provides a method of reading a ferroelectric integrated circuit memory element having two electrical terminals, the method comprising the steps of: connecting a first line at a first voltage to one of the terminals of the ferroelectric memory element while a second voltage is applied to the other terminal of the ferroelectric memory element to create a voltage across the ferroelectric memory element and to cause linear displacement current to flow from the ferroelectric memory element to the first line; increasing the voltage across the ferroelectric memory element by drawing off at least a portion of the linear displacement current from the first line; and completing the reading of the ferroelectric memory element. Preferably, the step of connecting also causes ferroelectric switching current to flow from the ferroelectric memory element to the first line and the step of increasing further comprises drawing off a portion of the switching current from the first line. Preferably, the step of drawing off comprises connecting the first line to a current source/sink via a transistor having a gate and applying a voltage boosted above the supply voltage of the memory to the gate. Preferably, the step of connecting the first line to a current source/sink comprises connecting first line to a ground. Preferably, the step of connecting the first line at the first voltage comprises connecting the first line at zero voltage.
In still a further, aspect the invention provides a method of creating an increased switching voltage across a ferroelectric memory element in a ferroelectric memory, the ferroelectric memory element having two terminals, the method comprising the steps of: connecting a bit line to a current source/sink via a precharge transistor having a gate; applying a precharge signal to the gate, the precharge signal being boosted above the supply voltage of the memory; and connecting the bit line to one of the electrodes of the ferroelectric memory element while a second voltage is applied to the other electrode of the ferroelectric memory element to create the switching voltage across the ferroelectric memory element. Preferably, the bit line to a current source/sink comprises connecting the bit line to a ground. Preferably, the step of connecting the bit line to one of the electrodes comprises connecting the bit line to the one of the electrodes via a transistor having a gate and applying a word line signal to the gate, the word line signal being boosted above the supply voltage of the memory.
The invention also provides a method of creating an increased switching voltage across a ferroelectric memory element in a ferroelectric memory, the ferroelectric memory element having two terminals, the method comprising the steps of: connecting a conducting line to a current source/sink via a precharge switch to remove charge from the conducting line; connecting the conducting line to one of the terminals of the ferroelectric memory element while a second voltage is applied to the other terminal of the ferroelectric memory element to create the switching voltage across the ferroelectric memory element; and disconnecting the conducting line from the current source/sink and stopping the removal of charge from the conducting line before any significant amount of the ferroelectric material switches. Preferably, the step disconnecting comprises stopping the removal of charge from the conducting line when the voltage across the ferroelectric memory element reaches its maximum.
The invention not only increases the switching voltage to essentially the full supply voltage, but does so with no change in the memory cell and little change in the memory circuitry external of the memory cell. In the preferred embodiment, only the timing of the precharge signal is changed. Thus, the invention can be readily applied to state-of-the-art ferroelectric memories at little expense. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.